| 1 | --- ../gcc-4.0.3/gcc/config/rs6000/darwin-fallback.c.orig 2007-11-11 10:46:12.000000000 +0900 |
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| 2 | +++ ../gcc-4.0.3/gcc/config/rs6000/darwin-fallback.c 2007-11-11 11:25:18.000000000 +0900 |
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| 3 | @@ -261,9 +261,9 @@ |
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| 4 | }; |
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| 5 | |
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| 6 | #define UC_FLAVOR_SIZE \ |
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| 7 | - (sizeof (struct mcontext) - sizeof (ppc_vector_state_t)) |
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| 8 | + (sizeof (struct __darwin_mcontext) - sizeof (ppc_vector_state_t)) |
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| 9 | |
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| 10 | -#define UC_FLAVOR_VEC_SIZE (sizeof (struct mcontext)) |
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| 11 | +#define UC_FLAVOR_VEC_SIZE (sizeof (struct __darwin_mcontext)) |
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| 12 | |
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| 13 | #define UC_FLAVOR64_SIZE \ |
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| 14 | (sizeof (struct gcc_mcontext64) - sizeof (ppc_vector_state_t)) |
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| 15 | @@ -354,33 +354,33 @@ |
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| 16 | } |
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| 17 | else |
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| 18 | { |
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| 19 | - struct mcontext *m = uctx->uc_mcontext; |
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| 20 | + struct __darwin_mcontext *m = (struct __darwin_mcontext *)uctx->uc_mcontext; |
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| 21 | int i; |
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| 22 | |
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| 23 | - float_state = &m->fs; |
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| 24 | - vector_state = &m->vs; |
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| 25 | + float_state = &m->__fs; |
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| 26 | + vector_state = &m->__vs; |
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| 27 | |
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| 28 | - new_cfa = m->ss.r1; |
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| 29 | + new_cfa = m->__ss.__r1; |
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| 30 | |
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| 31 | - set_offset (CR2_REGNO, &m->ss.cr); |
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| 32 | + set_offset (CR2_REGNO, &m->__ss.__cr); |
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| 33 | for (i = 0; i < 32; i++) |
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| 34 | - set_offset (i, &m->ss.r0 + i); |
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| 35 | - set_offset (XER_REGNO, &m->ss.xer); |
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| 36 | - set_offset (LINK_REGISTER_REGNUM, &m->ss.lr); |
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| 37 | - set_offset (COUNT_REGISTER_REGNUM, &m->ss.ctr); |
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| 38 | + set_offset (i, &m->__ss.__r0 + i); |
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| 39 | + set_offset (XER_REGNO, &m->__ss.__xer); |
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| 40 | + set_offset (LINK_REGISTER_REGNUM, &m->__ss.__lr); |
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| 41 | + set_offset (COUNT_REGISTER_REGNUM, &m->__ss.__ctr); |
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| 42 | |
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| 43 | if (is_vector) |
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| 44 | - set_offset (VRSAVE_REGNO, &m->ss.vrsave); |
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| 45 | + set_offset (VRSAVE_REGNO, &m->__ss.__vrsave); |
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| 46 | |
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| 47 | /* Sometimes, srr0 points to the instruction that caused the exception, |
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| 48 | and sometimes to the next instruction to be executed; we want |
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| 49 | the latter. */ |
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| 50 | - if (m->es.exception == 3 || m->es.exception == 4 |
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| 51 | - || m->es.exception == 6 |
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| 52 | - || (m->es.exception == 7 && !(m->ss.srr1 & 0x10000))) |
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| 53 | - return_addr = m->ss.srr0 + 4; |
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| 54 | + if (m->__es.__exception == 3 || m->__es.__exception == 4 |
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| 55 | + || m->__es.__exception == 6 |
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| 56 | + || (m->__es.__exception == 7 && !(m->__ss.__srr1 & 0x10000))) |
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| 57 | + return_addr = m->__ss.__srr0 + 4; |
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| 58 | else |
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| 59 | - return_addr = m->ss.srr0; |
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| 60 | + return_addr = m->__ss.__srr0; |
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| 61 | } |
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| 62 | |
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| 63 | fs->cfa_how = CFA_REG_OFFSET; |
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| 64 | @@ -399,14 +399,14 @@ |
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| 65 | set_offset (ARG_POINTER_REGNUM, &return_addr); |
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| 66 | |
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| 67 | for (i = 0; i < 32; i++) |
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| 68 | - set_offset (32 + i, float_state->fpregs + i); |
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| 69 | - set_offset (SPEFSCR_REGNO, &float_state->fpscr); |
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| 70 | + set_offset (32 + i, float_state->__fpregs + i); |
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| 71 | + set_offset (SPEFSCR_REGNO, &float_state->__fpscr); |
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| 72 | |
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| 73 | if (is_vector) |
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| 74 | { |
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| 75 | for (i = 0; i < 32; i++) |
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| 76 | - set_offset (FIRST_ALTIVEC_REGNO + i, vector_state->save_vr + i); |
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| 77 | - set_offset (VSCR_REGNO, vector_state->save_vscr); |
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| 78 | + set_offset (FIRST_ALTIVEC_REGNO + i, vector_state->__save_vr + i); |
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| 79 | + set_offset (VSCR_REGNO, vector_state->__save_vscr); |
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| 80 | } |
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| 81 | |
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| 82 | return true; |
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