Ticket #10976: Portfile

File Portfile, 893 bytes (added by oksmith77, 14 years ago)

Portfile for Veriwell

Line 
1# $Id$
2
3PortSystem       1.0
4name             veriwell
5version          2.8.5
6categories       science
7description      VeriWell Verilog Simulator
8
9long_description \
10     VeriWell is a full Verilog simulator. It supports nearly all of the \
11     IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the \
12     same simulator that was sold by Wellspring Solutions in the mid-1990 \
13     and was included with the Thomas and Moorby book
14   
15homepage         http://sourceforge.net/projects/veriwell
16platforms        darwin
17master_sites     sourceforge
18checksums        md5 1c1c6fb05009172d2677e34f0e511a37
19distname         ${name}-${version}
20depends_lib      port:help2man
21
22#  The following prevent conflicts with other Verilog simulators
23#  that may have installed their own copies of:
24#  acc_user.h  veriuser.c  veriuser.h
25
26configure.args  --includedir=${prefix}/include/veriwell
27