| 1 | # -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4 |
|---|
| 2 | # $Id$ |
|---|
| 3 | |
|---|
| 4 | PortSystem 1.0 |
|---|
| 5 | name iverilog |
|---|
| 6 | version 0.9.1 |
|---|
| 7 | categories science |
|---|
| 8 | maintainers none@none.com |
|---|
| 9 | description Icarus Verilog |
|---|
| 10 | long_description \ |
|---|
| 11 | Icarus Verilog is a Verilog simulation and synthesis tool. \ |
|---|
| 12 | It operates as a compiler, compiling source code writen in \ |
|---|
| 13 | Verilog (IEEE-1364) into some target format. For batch \ |
|---|
| 14 | simulation, the compiler can generate C++ code that is \ |
|---|
| 15 | compiled and linked with a run time library (called \"vvm\") \ |
|---|
| 16 | then executed as a command to run the simulation. \ |
|---|
| 17 | For synthesis, the compiler generates netlists in the desired format. |
|---|
| 18 | homepage http://www.icarus.com/eda/verilog/ |
|---|
| 19 | platforms darwin |
|---|
| 20 | |
|---|
| 21 | master_sites ftp://ftp.icarus.com/pub/eda/verilog/v0.9/ |
|---|
| 22 | distname verilog-${version} |
|---|
| 23 | checksums md5 91e8f40d995bf5ded7b847fcc02a98bf \ |
|---|
| 24 | sha1 dc68169c77ef036de6cf7798c665f1a82a4e4254 \ |
|---|
| 25 | rmd160 1eed8ff116ef81e0f1c6ab98eac58842e4325348 |
|---|
| 26 | |
|---|
| 27 | configure.args mandir=\\\${prefix}/share/man |
|---|
| 28 | destroot.destdir prefix=${destroot}${prefix} |
|---|
| 29 | test.run yes |
|---|
| 30 | test.target check |
|---|
