source: trunk/dports/science/vbs/Portfile

Last change on this file was 103723, checked in by jmr@…, 4 years ago

vbs: license

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 1.0 KB
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1# $Id: Portfile 103723 2013-03-05 19:18:15Z ryandesign@macports.org $
2
3PortSystem 1.0
4
5name             vbs
6version          1.4.0
7categories       science
8license          GPL-2+
9maintainers      nomaintainer
10description      Verilog Behavioral Simulator
11long_description \
12    This is the public release of the Verilog Behavioral Simulator. \
13    Verilog is a Hardware Description Language used mostly for digital \
14    circuit design and simulation.  This program is a simple \
15    implementation of a Verilog simulator.  VBS tries to implement all \
16    of the Verilog behavioral constructs that are synthesizable, but \
17    still allow complex test vectors for simulation.
18homepage         http://www.flex.com/~jching/
19platforms        darwin
20master_sites     ${homepage} http://www.geda.seul.org/dist/
21checksums        md5 07619d3dbfc030639d8ed1271f792d62
22worksrcdir       ${distname}/src
23
24patchfiles       patch-Makefile.in
25configure.args   --disable-debug
26build.target     ${name}
27test.run         yes
28test.target      test-all testv-all
29destroot.destdir prefix=${destroot}${prefix}
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