# $Id: Portfile,v 1.4 2005/04/16 20:51:13 toby Exp $

PortSystem 1.0
name             iverilog
version          0.8
categories       science
maintainers      toby@opendarwin.org
description      Icarus Verilog
long_description \
    Icarus Verilog is a Verilog simulation and synthesis tool. It \
    operates as a compiler, compiling source code writen in Verilog \
    (IEEE-1364) into some target format. For batch simulation, the \
    compiler can generate C++ code that is compiled and linked with \
    a run time library (called \"vvm\") then executed as a command to \
    run the simulation. For synthesis, the compiler generates netlists \
    in the desired format.
homepage         http://www.icarus.com/eda/verilog/
platforms        darwin

master_sites     ftp://icarus.com/pub/eda/verilog/v${version}/
distname         verilog-${version}
checksums        md5 12a20a7f63183e767a9d7d077eb0556c

patchfiles       patch-config.h.in patch-svector.h patch-vvp__stop.cc

configure.args   mandir=\\\${prefix}/share/man

test.run         yes
test.target      check

destroot.destdir prefix=${destroot}${prefix}