# $Id: Portfile 24137 2007-04-17 09:10:32Z ryandesign@macports.org $

PortSystem       1.0
name             veriwell
version          2.8.5
categories       science
maintainers	 nomaintainer@macports.org
description      VeriWell Verilog Simulator

long_description \
     VeriWell is a full Verilog simulator. It supports nearly all of the \
     IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the \
     same simulator that was sold by Wellspring Solutions in the mid-1990 \
     and was included with the Thomas and Moorby book
    
homepage         http://sourceforge.net/projects/veriwell
platforms        darwin
master_sites     sourceforge
checksums        md5 1c1c6fb05009172d2677e34f0e511a37
distname         ${name}-${version}
depends_lib      port:help2man

#  The following prevent conflicts with other Verilog simulators
#  that may have installed their own copies of:
#  acc_user.h  veriuser.c  veriuser.h

configure.args  --includedir=${prefix}/include/veriwell