# $Id: Portfile,v 1.2 2004/03/05 02:49:53 toby Exp $

PortSystem 1.0
name             iverilog
version          20040220
distname         verilog-${version}
categories       science
maintainers      toby@opendarwin.org
description      Icarus Verilog
long_description \
    Icarus Verilog is a Verilog simulation and synthesis tool. It \
    operates as a compiler, compiling source code writen in Verilog \
    (IEEE-1364) into some target format. For batch simulation, the \
    compiler can generate C++ code that is compiled and linked with \
    a run time library (called \"vvm\") then executed as a command to \
    run the simulation. For synthesis, the compiler generates netlists \
    in the desired format.
homepage         http://www.icarus.com/eda/verilog/
platforms        darwin
master_sites     ftp://icarus.com/pub/eda/verilog/snapshots/
checksums        md5 208d579866e9904a385296220104dcb2
configure.args   mandir=\\\${prefix}/share/man
destroot.destdir prefix=${destroot}${prefix}

test.run         yes
test.target      check