| 1 | # -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4 |
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| 2 | # $Id$ |
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| 3 | |
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| 4 | PortSystem 1.0 |
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| 5 | PortGroup python 1.0 |
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| 6 | |
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| 7 | name py-pyverilog |
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| 8 | version 0.9.6 |
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| 9 | categories-append devel |
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| 10 | license Apache-2 |
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| 11 | maintainers prosou.nu:yasu |
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| 12 | supported_archs noarch |
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| 13 | |
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| 14 | description Python based hardware design processing toolkit for Verilog HDL |
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| 15 | long_description \ |
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| 16 | Pyverilog is an open-source hardware design processing toolkit for \ |
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| 17 | Verilog HDL. All source codes are written in Python. \ |
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| 18 | Pyverilog includes (1) code parser, (2) dataflow analyzer, \ |
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| 19 | (3) control-flow analyzer and (4) code generator.\ |
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| 20 | You can create your own design analyzer, code translator and \ |
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| 21 | code generator of Verilog HDL based on this toolkit. |
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| 22 | |
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| 23 | platforms darwin |
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| 24 | |
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| 25 | homepage https://github.com/PyHDI/Pyverilog |
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| 26 | master_sites https://pypi.python.org/packages/source/p/pyverilog/ |
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| 27 | distname pyverilog-${version} |
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| 28 | |
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| 29 | checksums md5 1221113d4904973da10d7e6653ac041a \ |
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| 30 | sha256 cdb36aee241e6b1f17101a4a9008fad9cd98cbad72b2d55f4718083439a3e90b \ |
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| 31 | rmd160 3cc3d75f0bfc82dfd99b793da01206ce0f7a4f51 |
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| 32 | |
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| 33 | python.versions 27 33 34 |
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| 34 | |
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| 35 | if {$subport ne $name} { |
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| 36 | depends_lib port:py${python.version}-setuptools |
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| 37 | livecheck.type none |
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| 38 | } else { |
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| 39 | livecheck.type regex |
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| 40 | livecheck.url https://pypi.python.org/pypi/pyverilog/ |
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| 41 | livecheck.regex {pyverilog ([0-9\.]+)} |
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| 42 | } |
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